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Information
| Code | CEN263 |
| Name | Digital Design |
| Term | 2024-2025 Academic Year |
| Semester | 3. Semester |
| Duration (T+A) | 3-0 (T-A) (17 Week) |
| ECTS | 4 ECTS |
| National Credit | 3 National Credit |
| Teaching Language | İngilizce |
| Level | Lisans Dersi |
| Type | Normal |
| Mode of study | Yüz Yüze Öğretim |
| Catalog Information Coordinator | Dr. Öğr. Üyesi Barış ATA |
| Course Instructor |
Yunus Emre ÇOGURCU
(A Group)
(Ins. in Charge)
|
Course Goal / Objective
An introductory course in digital design, covering combinational and sequential circuits, memory and logic arrays and introduction to processor architecture, with a weekly lab. The SystemVerilog hardware description language is used throughout the semester to model and implement digital designs.
Course Content
Number systems, Binary numbers, Logic levels, transistors, gates, Boolean expressions. Combinational logic: Boolean algebra, simplification of Boolean expressions. Logic minimization with Karnaugh maps, don't-care conditions. Introduction to SystemVerilog. Combinational building blocks, multiplexers, decoders, propagation delays. SystemVerilog modeling. Sequential logic: SR latch, D-latch, D flip-flop, synchronous sequential circuits. Finite State Machine (FSM) design, Moore and Mealy models, state encodings, timing of sequential circuits. SystemVerilog modeling of sequential circuits. Signed numbers, Adders, ALU. Registers, counters, timers. RTL design, RAM, ROM. Introduction to general purpose processor architecture.
Course Precondition
None
Resources
David Money Harris, Sarah L. Harris, Digital Design and Computer Architecture, 2nd ed. Morgan Kaufmann, 2012. (Textbook)
Notes
Frank Vahid, Digital Design with RTL Design, VHDL and Verilog, 2nd ed. John Wiley, 2011. (Recommended)
Course Learning Outcomes
| Order | Course Learning Outcomes |
|---|---|
| LO01 | Ability to apply arithmetic in various number systems |
| LO02 | Ability to use Boolean Algebra to simplify logic circuit designs, to use Karnaugh maps to simplify logic circuit designs |
| LO03 | Ability to design combinational and sequential logic circuits. Ability to design synchronous sequential counters. Being able to design finite state machines in their simplest form. |
| LO04 | Modelling of combinational and sequential logic circuits with SystemVerilog. Signed numbers, adders, ALU. Registers, counters, timers. RTL design, RAM, ROM. Introduction to general purpose processor architecture. |
Relation with Program Learning Outcome
| Order | Type | Program Learning Outcomes | Level |
|---|---|---|---|
| PLO01 | Bilgi - Kuramsal, Olgusal | Adequate knowledge of mathematics, science and related engineering disciplines; ability to use theoretical and applied knowledge in these fields in solving complex engineering problems. | |
| PLO02 | Bilgi - Kuramsal, Olgusal | Ability to identify, formulate and solve complex engineering problems; ability to select and apply appropriate analysis and modeling methods for this purpose. | 5 |
| PLO03 | Bilgi - Kuramsal, Olgusal | Ability to design a complex system, process, device or product to meet specific requirements under realistic constraints and conditions; ability to apply modern design methods for this purpose. | |
| PLO04 | Bilgi - Kuramsal, Olgusal | Ability to select and use modern techniques and tools necessary for the analysis and solution of complex problems encountered in engineering practice; ability to use information technologies effectively. | |
| PLO05 | Bilgi - Kuramsal, Olgusal | Ability to design and conduct experiments, collect data, analyze and interpret results to investigate complex engineering problems or discipline-specific research topics. | 4 |
| PLO06 | Bilgi - Kuramsal, Olgusal | Ability to work effectively in interdisciplinary and multidisciplinary teams; individual working skills. | |
| PLO07 | Bilgi - Kuramsal, Olgusal | Ability to communicate effectively verbally and in writing; knowledge of at least one foreign language; ability to write effective reports and understand written reports, prepare design and production reports, make effective presentations, and give and receive clear and understandable instructions. | |
| PLO08 | Bilgi - Kuramsal, Olgusal | Awareness of the necessity of lifelong learning; ability to access information, follow developments in science and technology, and constantly renew oneself. | |
| PLO09 | Bilgi - Kuramsal, Olgusal | Knowledge of ethical principles, professional and ethical responsibility, and standards used in engineering practice. | |
| PLO10 | Bilgi - Kuramsal, Olgusal | Knowledge of business practices such as project management, risk management and change management; awareness of entrepreneurship and innovation; knowledge of sustainable development. | |
| PLO11 | Bilgi - Kuramsal, Olgusal | Knowledge of the effects of engineering practices on health, environment and safety in universal and social dimensions and the problems of the age reflected in the field of engineering; awareness of the legal consequences of engineering solutions. |
Week Plan
| Week | Topic | Preparation | Methods |
|---|---|---|---|
| 1 | Number systems, Binary numbers, Logic levels, transistors, gates, Boolean expressions | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 2 | Combinational logic: Boolean algebra, simplification of Boolean expressions | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 3 | Karnaugh Maps (K-Maps) for Simplification. Minimization Techniques for Boolean Expressions | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 4 | Combinational building blocks, multiplexers, decoders, propagation delays. Introduction to Verilog & SystemVerilog | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 5 | Sequential logic: SR latch, D-latch, D flip-flop, synchronous sequential circuits. Verilog & SystemVerilog modeling | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 6 | Registers and Counters | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 7 | Timing and Control Circuits. Clock Signals, Timing Diagrams | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 8 | Mid-Term Exam | Exam preparation | Ölçme Yöntemleri: Yazılı Sınav |
| 9 | Finite State Machine (FSM) design, Moore and Mealy models | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 10 | Memory and Programmable Logic Devices (PLDs). Memory Types: ROM, RAM, SRAM, DRAM | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 11 | Arithmetic Circuits: Binary Multipliers and ALU Design | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 12 | Combining Combinational and Sequential Circuits. Hierarchical Design Approach-1 | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 13 | Combining Combinational and Sequential Circuits. Hierarchical Design Approach-2 | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 14 | Combining Combinational and Sequential Circuits. Hierarchical Design Approach-3 | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 15 | Reading | Reading corresponding chapter of the text book | Öğretim Yöntemleri: Anlatım |
| 16 | Term Exams | Exam preparation | Ölçme Yöntemleri: Yazılı Sınav |
| 17 | Term Exams | Exam preparation | Ölçme Yöntemleri: Yazılı Sınav |
Student Workload - ECTS
| Works | Number | Time (Hour) | Workload (Hour) |
|---|---|---|---|
| Course Related Works | |||
| Class Time (Exam weeks are excluded) | 14 | 3 | 42 |
| Out of Class Study (Preliminary Work, Practice) | 14 | 3 | 42 |
| Assesment Related Works | |||
| Homeworks, Projects, Others | 0 | 0 | 0 |
| Mid-term Exams (Written, Oral, etc.) | 1 | 7 | 7 |
| Final Exam | 1 | 18 | 18 |
| Total Workload (Hour) | 109 | ||
| Total Workload / 25 (h) | 4,36 | ||
| ECTS | 4 ECTS | ||